An integrated circuit (“IC”) is a device (e.g., a semiconductor device) or electronic system that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect the IC's electronic and circuit components.
Design engineers design ICs by transforming logical or circuit descriptions of the ICs' components into geometric descriptions, called design layouts. Design layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with pins and (2) interconnect lines (i.e., geometric representations of wiring) that connect the pins of the circuit modules. In this fashion, design layouts often describe the behavioral, architectural, functional, and structural attributes of the IC. To create design layouts, design engineers typically use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, analyzing, and verifying design layouts. The applications also render the layouts on a display device or to storage for displaying later.
Fabrication foundries (“fabs”) manufacture ICs based on the design layouts using a photolithographic process. Photolithography is an optical printing and fabrication process by which patterns on a photolithographic mask (i.e., “photomask,” or “mask”) are imaged and defined onto a photosensitive layer coating a substrate. To fabricate an IC, photomasks are created using the IC design layout as a template. The photomasks contain the various geometries or shapes of the IC design layout. The various geometries or shapes contained on the photomasks correspond to the various base physical IC elements that comprise functional circuit components such as transistors, interconnect wiring, vertical interconnect access (via) pads, as well as other elements that are not functional circuit elements but are used to facilitate, enhance, or track various manufacturing processes. Through sequential use of the various photomasks corresponding to a given IC in an IC fabrication process, a large number of material layers of various shapes and thicknesses with various conductive and insulating properties may be built up to form the overall IC and the circuits within the IC design layout.
The process of producing these circuit components and/or wiring on an IC often results in circuit components and/or wiring that have different heights for the same layer of the IC. Because an IC typically has several layers that are stacked one on top of each other, it is desirable to have circuit components and/or wiring to have the same height along the entire layer of the IC (i.e., to have a flat surface along the entire layer). This ensures that subsequently placed layers of the IC remain parallel to the other layers of the IC.
To produce a layer of an IC with a flat surface (e.g., global planarization of the layer), a chemical mechanical polishing (“CMP”) process is performed after the circuit components and/or wiring are produced on a layer of the IC. As the name implies, a CMP process is a procedure that polishes the layers of the IC to flatten the surface of the layer of the IC. Typically, the CMP process uses an abrasive and/or corrosive slurry that removes excess topological features (e.g., circuit components that extend beyond a certain height above the surface of a particular layer) of the layers of the IC.
However, CMP is a density sensitive process. In particular, the CMP requires that the density of the layer of the IC be within a minimum and maximum range. In other words, for the CMP process to be effective, the density of the IC layer has to be within a particular density range. Ideally, the density of the layer should be uniform throughout the entire layer. The density of the IC layer can be defined as the total area of the circuit components and wiring divided by the total area of the IC layer. When the density of the layer is not uniform or is not within the particular range, some of the side effects of the CMP process may include removing essential topological features (e.g., circuit elements) of the IC layer.
To resolve this issue, design engineers insert fills in certain regions of the IC layer in the design layout to create uniform density throughout the entire IC layer and/or to ensure that local regions of the IC layers meet the minimum density values for the CMP process. When fabricated, these fills are inactive and non-functional materials that are inserted between wiring and circuit components.
To prepare a design layout with fills inserted, design engineers have been following a typical process as illustrated in FIG. 1 using EDA applications. FIG. 1 conceptually illustrates a process 100 that one or more EDA applications perform to produce a design layout. The process 100 will be described by reference to FIG. 2 which conceptually illustrates in six different stages 201-206 a region 200 of a design layout that is being changed as the process 100 is being performed. The process 100 starts when the process receives logical or circuit descriptions of the IC's components.
The process 100 begins by performing placing and routing (at 105). As the name suggests, placing and routing involves two operations—placing and routing. In the placing operation, the process 100 converts the circuit representation of the IC into a geometric representation of the IC (i.e., a design layout of the IC). Specifically, the process 100 identifies the position of geometries (e.g., circuit modules geometries) or shapes on the design layout. The process 100 also abides by a set of design rules (e.g., minimum spacing rule which defines a minimum distance for two adjacent shapes to have in a design layout) when identifying the positions of the shapes. The process 100 performs the placing operation based on information contained in a design file (e.g., LEF/DEF file). A design file contains information regarding the physical design of the IC.
After performing the placement operation, the process performs a routing operation. In the routing operation, the process 100 specifies different regions in the routing space through which a wire (i.e., a net) should be routed. The process 100 also defines routes that connect the routable elements (e.g., pins) in the layout. The process 100 defines the routes while abiding by a set of design rules.
The process 100 identifies (at 110) one or more potential critical nets without knowing where the fill shapes will be placed in the design layout. That is, the process 100 identifies the potential critical nets without considering the locations of the fills to be placed in the design layout. A critical net is a net of which the timing is “critical” for several different reasons. For instance, a net is a critical net when the required delay of the net for the circuit to function properly is shorter than the actual delay of the net. That is, a net is critical when the time the net takes to transmit a signal is longer than the required time for the circuit to function properly. Such a net has a negative slack because the slack computed by subtracting the actual delay from the required delay has a negative value. A net is also a critical net when the circuit's proper functioning is sensitive to signal delays of the net. For instance, a clock net that is to transmit a clock signal is a critical net because the circuit's proper functionality will be affected by even a small amount of delay of the clock signal. Similarly, an analog net that is to transmit an analog signal is a critical net. The process 100 identifies, as potential critical nets, the nets that have negative slacks, the nets that will likely have negative slacks once the fills are placed near the nets (i.e., the nets that have small positive slacks), and the nets that are critical for other reasons (e.g., a clock net).
Next, the process 100 places (at 115) fills between the nets of the design layout but away from the potential critical nets identified at 110 in order to avoid making the delays of the potential critical nets longer. The process 100 places fills farther away from the identified nets than from other nets which are not deemed critical. The process 100 defines a distance within which the fills should not be placed from the identified nets. The process 100 defines this distance based on estimation of (i.e., prediction on) the impact of the fills on the delays of the identified nets. The process 100 may also define a region around the identified nets and does not place fills within the defined region. The process 100 defines the region based on estimation of the impact of the fills on the delays of the identified nets. When defining the distance or the region, the process 100 uses a fixed strategy. For instance, the process 100 defines a first distance for the nets in a first layer of the design layout and defines a second distance for the nets in a second layer of the design layout.
Stage 201 of FIG. 2 illustrates that the region 200 of the design layout includes two nets 210 and 215. At stage 202, the net 210 is colored black to conceptually indicate that the net 210 is identified as a potential critical net. Stage 203 illustrates that a region 220, depicted as a dotted rectangle, is defined around the net 210 based on an estimation of the impact of the fills on the delays of the net 210. The region 220 is defined such that the fills, depicted as white rectangles, are placed farther away from the net 210 than from the net 215. As shown, no fills are placed within the region 220 around the net 210. As a result, the fills are farther away from the net 210 than from the net 215.
Next, the process 100 performs (at 120) RC extraction and timing analysis. That is, the process 100 extracts resistance and capacitance information from the design layout, and use the extracted information to verify that the design of the IC meets certain operational requirements. These requirements include performance objectives and physical constraints. For example, a net may have a required delay of a signal passing through the net. The process 100 computes the actual delay of the signal based on the extracted information and compares the actual delay with the required delay to determine whether the actual delay satisfies the required delay. Stage 204 of FIG. 2 conceptually illustrates RC extraction. As shown, resistances parasitic to the nets and fills and the parasitic capacitances between the nets and the fills are conceptually illustrated as resistor and capacitor symbols.
The process 100 then determines (at 125) whether there is a timing violation in the design layout. The process 100 determines that there is a timing violation when there is a net whose actual delay is longer than the net's required delay. The process 100 determines that there is no timing violation when no net has an actual delay that is longer than the net's required delay. When the process 100 determines (at 125) that there is no timing violation, the process ends. When the process 100 determines (at 125) that there is a timing violation, the process loops back to 110 to perform operations 110-120 again to remedy the timing violation. Stages 205 of FIG. 2 illustrates that the net 215 has been identified as a critical net. Stage 206 illustrates that a region 225 is defined around the net 215 and no fills are placed within the region 225.
As illustrated in FIG. 1, the process 100 may have to perform several iterations of operations 110-120 in order to fix all timing violations. Taking several iterations of these operations consumes much time because identifying potential critical nets 110, inserting fills away from the potential critical nets 115, and the RC extraction and timing analysis 115 are typically time-consuming operations to perform. The process 100 in some cases has to go back 105 when several iterations of operations 110-120 cannot fix the timing violations.
Moreover, the likelihood of having to perform multiple iterations of operations 110-120 is high for several reasons. First, the distance from the critical nets defined at 115 to place the fills away from the critical nets may not be accurate because the distance is defined based on an estimation of impact of the fills on the delays of the critical nets. Second, identifying too many regions from which to exclude fills in operation 115 may not leave enough room in the design layout in which to put fills to meet the minimum density for a region of the design layout. Third, in the operation 110, guessing on timing impact of fills on nets may result in identifying the wrong nets as potential critical nets and placing fills near the actual critical nets. As shown in FIG. 2, the net 215 has turned out to be a critical net after placing the fills in the design layout. Also, the net 210 has turned out to be a non-critical net after placing the fills.